Job Description :
Vacancies & Eligibility Criteria:
|Senior SoC RTL Design Engineer||N/A||N/A||Graduate||as per norms|
Dates to Consider
Last date for final submission of Application: ASAP
BS degree or higher in EE or CE or CS
10+ years or more of practical semiconductor design experience including full-chip and subsystem integration
Experience in micro-architecture definition from architecture guideline and model analysis.
Experience in RTL coding (Verilog/System Verilog) and debug, as well as performance/power/area analysis and trade-offs
Experience in closing full-chip and subsystem timing working with synthesis and static timing analysis teams.
Successful tape-outs of complex, high-volume SoCs in advanced design nodes.
Experience with DFT tools for scan and BIST insertion
Excellent verbal and written communication skills, collaboration and teamwork skills as well as ability to contribute to diverse and inclusive teams.
In-depth knowledge of in one or more areas such as CPU, DSP, or programmable accelerators.
Design experience in Datapath, flow control, Arbitration, FIFO, DMA, IOMMU, SOC bus architectures, Arteris NOC interconnect, ARM’s AXI/AHB bus architecture & Protocols, Serial interfaces such as PCIe, QSPI, I2C, UART, EMMC, USB. LPDDR controller & Phy IP integration, embedded memory (SRAM, OTP etc;) . Other IP integration such as ADC, PLL, DLL, PVT sensors & Debug(Coresight)
SOC bring-up and post-silicon validation experience
Experience with RTL power analysis.
Experience with gate-level testing and multi-clock design practices.
Experience working with software teams to tightly define the HW/SW interface including control/status registers, and error handling.
Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance, and area.
How To Apply:
Interested candidates with qualifications may apply online for concerned posts as per the given online application form.
Keeping a print copy for future use is advised.
|Apply Online||Click Here|
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